System for converting hardware designs in high-level programming languages to hardware implementations

ABSTRACT

A computer aided hardware design system for enabling design of an actual hardware implementation for a digital circuit using a high-level algorithmic programming language. The system converts an algorithmic representation for a hardware design initially created in the high-level programming language, such as ANSI C, to a hardware design implementation, such as an FPGA or other programmable logic or an ASIC. The C-type program representative of the hardware design is compiled into a register transfer level (RTL) hardware description language (HDL) that can be synthesized into a gate-level hardware representation. The system additionally enables simulation of the HDL design to verify design functionality. Finally, various physical design tools can be utilized to produce an actual hardware implementation. The system also permits the use of other non-C-type high-level programming languages by first translating to a C-type program. In contrast to previous hardware design tools, the system compiles all C-type programming language features, including pointers and structures, into synthesizable HDL.

CROSS-REFERENCE TO MICROFICHE APPENDIX

[0001] Appendix A, which is a part of the present disclosure, is a microfiche appendix consisting of two sheets of microfiche having a total of 176 frames. Microfiche Appendix A is a source code listing of a portion of the code comprising one embodiment of a system for converting hardware designs in a high-level programming language (ANSI C) into a register transfer level hardware description language (Verilog), which is described in more detail below.

[0002] A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as they appear in the U.S. Patent and Trademark Office patent files or records, but otherwise reserves all copyright rights whatsoever.

FIELD OF THE INVENTION

[0003] This invention relates to configuring digital circuits, especially computationally intensive digital circuitry, such as field programmable gate arrays (FPGAs) and other programmable logic hardware and application specific integrated circuits (ASICs), and, more particularly, to computer aided design of such computationally intensive digital circuitry. Specifically, one embodiment of the invention provides a system for converting a hardware design rendered in a high-level programming language, such as ANSI C, into an actual hardware implementation, for example, as an FPGA.

[0004] Various persons have previously attempted to address the long-felt need for an easy approach to designing computationally intensive digital circuits, such as FPGAs. The prior art evidences two divergent approaches for designing actual implementations for digital hardware.

[0005] One prior art approach has been to create a specific hardware description language (HDL) for designing hardware. Various commercially available HDLs have been developed, such as Verilog, VHDL, ABEL, CUPL, AHDL, MACHX, and PALASM. After a hardware design is rendered in an HDL, the HDL design is processed into a gate-level hardware representation using one of various hardware- or manufacturer-specific synthesis programs to interpret the HDL design. Then, the gate-level representation is reduced to an actual hardware implementation using conventional physical design tools.

[0006] HDLs are specific computer aided design tools for hardware designers and require a level of expertise in the use of the particular HDL being employed to render a hardware design and are difficult to learn and use. See, for example, Tuck, B., “Raise Your Sights to the System Level,” Computer Design, June, 1997, pp. 53, 69. Therefore, only persons who frequently design hardware typically use HDLs. If a circuit application arises in which design and implementation of an FPGA is economically justified, the vast majority of persons must retain an expert or confront the difficult task of learning an HDL. Furthermore, these HDLs are not typically universal for the design of FPGAs, since many HDLs are supported by only a single or a limited number of hardware manufacturers. Consequently, even experienced users of an HDL, such as full-time hardware designers, may not be sufficiently familiar with other HDLs to be able to render a design which can be implemented in a variety of hardware systems from a number of different hardware manufacturers. There is therefore a need for an easy-to-use, universal computer aided hardware design tool by both experts and occasional hardware designers as well.

[0007] A second prior art approach recognizes that the development of computationally intensive hardware would be available to a wider population of persons if hardware designs could be rendered in a standard high-level programming language which is more universally known, easier to use, and more frequently employed than HDLs. One such high-level programming language is ANSI C. Others, many of which have several extensions, are: APL, Ada, Algol, B, Basic, Kernighan & Ritchie C, C++, CLOS, COBOL, Clu, Common Lisp, Coral, Dylan, Eiffel, Emacs Lisp, Forth, Fortran, IDL, Icon, Java, Jovial, Lisp, LOGO, ML, Modula, Oberon, Objective C, PL/I, PL/M, Pascal, Postscript, Prolog, Python, RTL, Rexx, SETL, Simula, Sather, Scheme, Smalltalk, Standard ML, TCL, and TRAC.

[0008] Unfortunately, prior art attempts to base computer aided hardware design tools on high-level programming languages have been incomplete. Consequently, these attempts to realize the goal of providing an effective tool for designing hardware using a high-level programming language have not achieved widespread use. All the prior art attempts have each suffered three or more of the following shortcomings:

[0009] 1. Prior art computer aided hardware design tools generate so many unhandled exceptions and language restrictions when presented with typical high-level language programs (e.g., a C program) that it renders such tools virtually useless for practical hardware design. Therefore, persons using such tools are required to read manuals and attempt to create work-arounds for portions of the high-level programming language, which are not implemented.

[0010] 2. Hardware generated using prior art computer aided hardware design tools is typically based on simple line-by-line, table-driven translation and as such does not contain the necessary widely scoped optimizations that produce practical and useful hardware designs for most applications.

[0011] 3. Design output of the prior art computer aided hardware design tool can be in so-called “behavioral HDL” for modeling hardware but in many cases cannot be synthesized by existing synthesis programs into a gate-level representation of the hardware.

[0012] 4. Prior art computer aided hardware design tools attempt to generate designs which only apply to a single manufacturer hardware family, such as the creation of an XNF file for the Xilinx XC4000 FPGA family.

[0013] 5. The language employed by prior art computer aided hardware design tools has added and limited so many constructs that it is difficult to consider the employed language as the high-level programming language purportedly being emulated. That is, the resultant language is more like a new specialized HDL.

[0014] Considered in more detail, one prior art computer aided hardware design tool which purports to enable persons to render hardware designs in a high-level programming language is Transmogrifier (TMCC), a tool developed in 1994-1995 at the University of Toronto, Canada. A comprehensive compiler typically requires at least ten times the 4,900 lines of code which comprise TMCC. TMCC does not support such common C-type programming language features as “do” loops, “for” loops, local or global arrays (i.e., the [ ] operator), the operators −>, unary &, unary *, etc.

[0015] Another prior art computer aided hardware design tool is NLC developed at Ecole Polytechnique Federale de Lausanne, Switzerland in 1994-1995. The code for NLC is based on the public domain compiler known as GNU. Like Transmogrifier, NLC supports a severely restricted subset of C-type programming language, for example, “for” loop bounds must be known at compile time, and functions cannot return values. The NLC library generates hardware designs only in XNF format for the Xilinx XC4000 FPGA family.

[0016] A prior art computer aided design tool for hardware which purports to be a high-level programming language is Handel-C, originally developed at the Computing Laboratory of Oxford University, England in 1995-1996 and presently supported by Embedded Solutions Limited in Berkshire, England. Although Handel-C has been described by its developers as a subset of ANSI C with some Occam-like extensions, the vast majority of ANSI C programs cannot be processed by Handel-C. For example, functions in Handel-C must be declared in main, have no return values, and have no parameters. There are no structs, unions, enums, struct bit fields, character constants, externs, pointers, etc. The output of Handel-C is in XNF format for the Xilinx XC4000 FPGA family. Since the language is so unlike a high-level programming language, Handel-C is better classified as an HDL for the Xilinx XC4000 FPGA family.

[0017] A further prior art computer aided hardware design tool is XC. XC was developed at Giga Operations Corporation in Berkeley, Calif. XC appears to be generally disclosed in Taylor, U.S. Pat. No. 5,535,342 issued on Jul. 9, 1996 and in Taylor et al., U.S. Pat. No. 5,603,043 issued on Feb. 11, 1997, both assigned to Giga Operations. There is little resemblance to C-type programming language. XC does not appear to implement structures, pointers, multidimensional arrays, unary &, unary *, etc., as evidenced by various examples published by Giga Operations at its web site. The output of XC is targeted only at the XC4000 board manufactured by Giga Operations that incorporates the Xilinx XC4000 FPGA family.

[0018] Finally, an analysis of the prior art would be incomplete without mention of the JRS ANSI C to VHDL Translator (JRS) developed at JRS Research Laboratories, Inc., Orange, Calif. in 1996. JRS appears to handle a wider range of high-level programming language features than other known prior art attempts but still lacks such standard features as multidimensional arrays, abstract declarators, automatic type conversions, pointers to arrays, pointers to functions, functions returning pointers, variable-length argument lists, and “goto” statements. An even more significant deficiency of JRS is that the output of JRS is in general not synthesizable VHDL. JRS utilizes constructs in VHDL considered “behavioral VHDL,” that are usefutl to describe hardware for simulation, but in general cannot be implemented into gate-level hardware representations by existing synthesis tools. As such, JRS is appropriately classified as a language translator, not a compiler that outputs realizable hardware designs. JRS does not address register transfer level (RTL) HDL problems of translating a high-level language to a hardware design.

[0019] Consequently, there is a long-felt but unsolved need for a system in which a hardware design can be rendered in a high-level programming language in a way to enable the full power of that language to be employed as a computer aided design tool for hardware. There is also a concomitant need for a computer aided design tool for hardware which is familiar and therefore easier to use than HDLs and which is nevertheless universal in that the resulting hardware designs can be implemented by a broad range of hardware manufacturers.

SUMMARY OF THE INVENTION

[0020] The present invention provides a solution to the problem of facilitating the design of an actual hardware implementation for digital circuits using a high-level programming language by providing in one embodiment a system for converting a C-type language program to a hardware design implementation, such as an FPGA or other programmable logic or an ASIC. A method in accordance with one embodiment of the invention comprises the steps of creating an algorithmic representation for a preliminary hardware design in a given C-type programming language and compiling the C-type programming language description into a register transfer level (RTL) hardware description language (HDL) design which can be synthesized. Preferably, the method of the invention additionally comprises the step of synthesizing the HDL design into a gate-level hardware representation using a conventional synthesis program to interpret the HDL design.

[0021] In order to produce an actual hardware implementation, the method in accordance with the invention preferably further comprises the step of using conventional physical design tools to implement the gate-level hardware representation as an actual hardware implementation. These physical design tools include a place and route program. In the case of an FPGA, the physical design tools also include a hardware configuration system which processes the file produced by the place and route program and creates a bit stream to personalize the FPGA. In the case of an ASIC, the physical design tools include a place and route program for creating a file for patterning an integrated circuit mask for use in fabricating the ASIC.

[0022] The C-type programming language used to render an algorithmic representation for the preliminary hardware design may be any standard C-type programming language including ANSI C, B, C++, Java, Kernighan & Ritchie C, and Objective C. The method of the invention is robust in that the method converts any typical hardware design rendered with the C-type programming language into a standard HDL. The standard HDLs include Verilog, VHDL, ABEL, CUPL, AHDL, MACHYX, and PALASM. The method in accordance with the invention first converts the preliminary hardware design to a register transfer level HDL, which enables the HDL design to be synthesized into a gate-level hardware representation using a standard synthesis program and then implemented as an actual hardware implementation using conventional physical design tools. In accordance with the invention, an embodiment of apparatus comprising a personal computer or workstation and executable code that implements the method of the invention is also provided.

[0023] The method in accordance with the invention can further comprise simulating the HDL synthesizable design prior to synthesizing the HDL design. Any conventional simulation program used to simulate a standard HDL design can be employed for simulating the hardware design converted from a rendition in C-type programming language to HDL. This enables the design originally rendered in a C-type programming language to be simulated and the design to be modified before the hardware is actually synthesized and implemented using conventional physical design tools. Consequently, hardware designs rendered in the C-type programming language can be optimized before the hardware implementation phase. Unlike the prior art, the method of the invention enables a hardware design originally rendered in a C-type programming language to be both simulated and implemented in an actual hardware implementation. The apparatus in accordance with the invention can also be utilized to simulate the HDL synthesizable design following compilation to HDL using code that executes the standard simulation program.

[0024] In a preferred embodiment of the method in accordance with the invention, compilation of the C-type programming language into HDL comprises mapping predetermined C-type programming language expressions to functionally equivalent HDL program language expressions, assigning input/output as defined in the C-type program to specific wires in the HDL synthesizable design, and configuring in the HDL synthesizable design an interface for the gate-level hardware representation. This is sufficient for basic hardware designs rendered in the C-type programming language.

[0025] Additionally, efficient conversion of basic hardware designs from the C-type programming language to HDL preferably entails compilation of a plurality of selected C-type functions that can execute simultaneously into a plurality of executable HDL program language expressions that operate in parallel. Efficient conversion fuirther entails compilation of a plurality of interdependent C-type functions into a plurality of executable HDL program language expressions that operate either simultaneously or sequentially in a data processing pipeline. Preferably, in order to effect efficient conversion, a callable C-type function is also compiled into an executable HDL program language expression that is executed either synchronously or asynchronously on the occurrence of an external event.

[0026] In the preferred embodiment of the method in accordance with the invention, compilation can comprise compiling a C-type program control flow into an HDL state machine. The method further comprises assigning input/output as defined in the C-type program to specific wires in the HDL synthesizable design and configuring in the HDL synthesizable design an interface for the gate-level hardware representation.

[0027] Also, the C-type program is preferably analyzed for determining the presence of any C-type pointers in the C-type program and compiling any C-type pointers and pointer indirection into an HDL state-machine-based memory access protocol. Therefore, unlike prior art computer aided hardware design tools, the method in accordance with the invention supports the use of memory structures and pointers typically employed in C-type programming language during the original rendering of the hardware design.

[0028] Additionally, the C-type program is preferably analyzed for determining the presence of any non-addressable variables in the C-type program and mapping any non-addressable variables onto hardware registers formed in HDL. Similarly, the C-type program is also analyzed for determining the presence of any addressable variables in the C-type program and mapping any addressable variables onto addressable hardware memory and/or an addressable array of hardware registers formed in HDL.

[0029] Finally, the C-type program is preferably analyzed for determining the presence of any complicated C-type mathematical operations in the C-type program and compiling multiple occurrences of any complicated C-type mathematical operation into a given HDL functional block that implements such an operation invoked on each occurrence by different states driven by the state machine. The complicated C-type mathematical operations include integer operations, such as signed and unsigned multiplication, signed and unsigned division, signed and unsigned remainder operation, variable-shift left shift, variable-shift right shift with or without sign extension, etc., and floating point operations, such as addition, subtraction, subtraction from zero (unary −), multiplication, division, and conversions involving floating point types. The given HDL functional block is effectively re-used to provide resource-sharing for conversion to an efficient HDL synthesizable design.

[0030] Preferably, compilation in accordance with the method of the invention employs state machines for efficient conversion from the C-type programming language to the HDL program language. More particularly, a plurality of selected C-type functions that can execute simultaneously are compiled into a plurality of HDL state machines that operate in parallel. A plurality of selected C-type functions that can execute simultaneously are further preferably compiled into a plurality of HDL state machines that operate in parallel. Also, a plurality of interdependent C-type functions are compiled into a plurality of executable HDL program language expressions that operate either simultaneously or sequentially in a data processing pipeline. A callable C-type function is also preferably compiled into at least one executable HDL state machine which is executed either synchronously or asynchronously on the occurrence of an external event.

[0031] Also in accordance with the present invention, a solution is provided to the problem of facilitating the design of an actual hardware implementation using any high-level programming language by providing in one embodiment a system for initially translating from an algorithmic representation for a hardware design in any given standard high-level programming language to an algorithmic representation for the hardware design in a C-type programming language and then converting the C-type language program to a hardware design implementation, such as an FPGA or other programmable logic or an ASIC. Standard high-level programming languages that can be translated to a C-type programming language utilizing conventional compilers include APL, Ada, Algol, B, Basic, Kernighan & Ritchie C, C++, CLOS, COBOL, Clu, Common Lisp, Coral, Dylan, Eiffel, Emacs Lisp, Forth, Fortran, IDL, Icon, Java, Jovial, Lisp, LOGO, ML, Modula, Oberon, Objective C, PL/I, PL/K Pascal, Postscript, Prolog, Python, RTL, Rexx, SETL, Simula, Sather, Scheme, Smalltalk, Standard ML, TCL, and TRAC.

[0032] Accordingly, the invention also provides in one embodiment a method which comprises the steps of creating an algorithmic representation for a preliminary hardware design in a given high-level programming language, translating the high-level programming language preliminary hardware design into an algorithmic representation for the preliminary hardware design in a C-type programming language, and compiling the C-type programming language description into a register transfer level HDL design which can be synthesized. Preferably, the method of the invention additionally comprises the step of synthesizing the HDL design into a gate-level hardware representation using a conventional synthesis program to interpret the HDL design. In order to produce an actual hardware implementation, the method in accordance with the invention preferably further comprises the step of using conventional physical design tools to implement the gate-level hardware representation as an actual hardware implementation.

[0033] The steps of compiling the C-type programming language description for the preliminary hardware design into an HDL synthesizable design and synthesizing the HDL design using a conventional synthesis program are identical to the steps performed if the hardware design were initially rendered in the C-type programming language. Also, the step of then implementing the gate-level representation resulting from synthesizing the HDL design as an actual hardware implementation using conventional physical design tools is identical to the step performed after synthesis in the case where the algorithmic representation for the hardware design was initially rendered in the C-type programming language. This enables hardware designs rendered in virtually any standard high-level programming language to be implemented in hardware. Also, the method can further comprise simulating the HDL synthesizable design prior to synthesizing the HDL design. In accordance with the invention, an embodiment of apparatus comprising a personal computer or workstation and executable code that implements the method of the invention is also provided.

[0034] The system in accordance with the invention has significant advantages compared to the purported high-level language computer aided hardware design tools known in the prior art. The system of the invention is the only ANSI C compiler. The system in accordance with the invention supports C-type programming language pointers and pointer arithmetic, variable argument functions, pointers to functions, recursion, structure assignment, and floating point arithmetic. The system of the invention also supports C-type programming language structures, unions, enums, and typedefs, as well as the complete set of C-type programming language control flow operators, including “for,” “while”, and “do” loops, “if”, “switch”, “break”, “continue”, “goto”, and “return”. The system in accordance with the invention also supports C char type, including strings literals, character constants, character arrays, and character pointers. All basic C integer types and type conversions are supported by the system of the invention, and the system follows ANSI C rules for integer promotion in operations. The system in accordance with the invention converts an ANSI C algorithmic representation for a hardware design to a synthesizable hardware design in HDL, such as Verilog, and, therefore, is compliant with multiple hardware technologies, whereas the known prior art computer aided hardware design tools generate hardware- and/or manufacturer-specific files, such as an XNF file for the Xilinx XC4000 FPGA family. Unlike prior art computer aided hardware design tools that generate “behavioral VHDL” models that can only be simulated, the system of the invention enables both simulation and synthesis that leads to an actual hardware implementation.

BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The above and other objectives and features and the concomitant advantages of the present invention will be better understood and appreciated by those skilled in the art in view of the description of the preferred embodiments given below in conjunction with the accompanying drawings. In the drawings:

[0036]FIG. 1 illustrates one embodiment of the computer aided hardware design tool for compiling C-type programming language into hardware description language (HDL) to enable conversion from a hardware design in a high-level programming language to a synthesizable HDL hardware design in accordance with the invention;

[0037]FIG. 2 is a flowchart of one embodiment of the method in accordance with the invention for compiling high-level programming language, such as C-type programming language, into HDL to enable conversion from a hardware design in a high-level programming language to a synthesizable HDL hardware design;

[0038] The remainder of the figures illustrates various examples of compilation of C-type programming language into a register transfer level (RTL) HDL to enable conversion from a hardware design in a high-level programming language to a synthesizable HDL hardware design by the computer aided hardware design tool in accordance with the invention shown in FIG. 1, specifically:

[0039]FIG. 3A shows an initial C-language description having simple expression functions (“func1” and “func2”);

[0040]FIG. 3B shows HDL created by compiling the C-type program shown in FIG. 3A, illustrating simple expression functions (“func1” and “func2”) which do not require state machines implemented in RTL Verilog;

[0041]FIG. 4A shows an initial C-language description having “non-simple” expression functions (“func1”, “func2”, and “func3”) using data conversions and “if-then-else” statements;

[0042]FIG. 4B shows HDL created by compiling “non-simple” expression functions (“func1”, “func2”, and “func3”) of the C-type program shown in FIG. 4A, which do not require state machines implemented in RTL Verilog;

[0043]FIG. 5A shows an initial C-language description using “for” loop expressions and non-addressable variables;

[0044]FIG. 5B, comprising FIGS. 5B1-5B4, shows HDL created by compiling the C-type program shown in FIG. 5A, including a “for” loop and non-addressable variables mapped into registers using a state machine implemented in RTL Verilog;

[0045]FIG. 6A shows an initial C-language description with input/output (I/O) function calls;

[0046]FIG. 6B shows HDL created by compiling ANSI C printf and scanf arguments of the C-type program shown in FIG. 6A into wire assignments in RTL Verilog;

[0047]FIG. 7A shows an initial C-language description with multiple occurrences of complicated mathematical operations;

[0048]FIG. 7B, comprising FIGS. 7B1-7B4, shows HDL created by compiling the C-type program shown in FIG. 7A into functional blocks in RTL Verilog for complicated mathematical operations invoked on each occurrence by different states of the generated state machine;

[0049]FIG. 8A shows an initial C-language description having interdependent C-type functions;

[0050]FIG. 8B shows HDL created by compiling the C-type program shown in FIG. 8A into a simple data processing pipeline implemented in RTL Verilog;

[0051]FIG. 8C is a block diagram of the data processing pipeline implemented in the RTL Verilog shown in FIG. 8B;

[0052]FIG. 9A shows an initial C-language description having floating point arithmetic;

[0053]FIG. 9B, comprising FIGS. 9B1-9B4, shows HDL created by compiling the C-type program shown in FIG. 9A, illustrating subtraction from zero (unary −), addition, multiplication, subtraction, division, and conversion operations involving floating point arithmetic in RTL Verilog;

[0054]FIG. 10A shows an initial C-language description of two complex number addition with structures, including structure assignments, structure function parameters, and structure function return values;

[0055]FIG. 10B, comprising FIGS. 10B1-110B5, shows HDL created by compiling the C-type program shown in FIG. 10A, illustrating structure function parameters and structure return values implemented in hardware registers in RTL Verilog;

[0056]FIG. 11A, comprising FIGS. 11A1-11A2, shows an initial C-language description having pointers and pointer indirection;

[0057]FIG. 11B, comprising FIGS. 11B1-11B8, shows HDL created by compiling the C-type program shown in FIG. 11A, illustrating a non-addressable variable “p” implemented in a hardware register, addressable variables “pTree” and “Nodes” implemented in memory locations identified by addresses of “'_pTree” and “'_Nodes” in externally addressable hardware memory, and “while” loops, “if-then-else” statements, “return” statements, and function calls in RTL Verilog;

[0058]FIG. 12A shows an initial C-language description with a callable function;

[0059]FIG. 12B shows HDL created by compiling the C-type program shown in FIG. 12A, illustrating detection of the event “event_occured” on the occurrence of the positive edge of a clock signal using “always” statements;

[0060]FIG. 13A shows an initial C-language description having a callable function and a pragma which directs compilation for asynchronous event detection;

[0061]FIG. 13B shows HDL created by compiling the C-type program shown in FIG. 13A, illustrating detection of the event “event_occured” when the signal “run-on-event” transitions from false to true, which occurs asynchronously with the positive edge of a clock signal;

[0062]FIG. 14A shows an initial C-language description with parallel processing of two complex functions (“func1” and “func2”) which do not interfere with each other;

[0063]FIG. 14B, comprising FIGS. 14B1-14B2, shows HDL created by compiling the C-type program shown in FIG. 14A, illustrating parallel processing of two complex non-interfering functions with two state machines implemented in RTL Verilog running simultaneously;

[0064]FIG. 15A shows an initial C-language description having variable argument function calls;

[0065]FIG. 15B, comprising FIGS. 15B1-15B7, shows HDL created by compiling the C-type program shown in FIG. 15A, illustrating variable argument function calls using a temporary parameter storage location in addressable memory implemented in RTL Verilog and using on-chip Xilinx RAM macros;

[0066]FIG. 16A shows an initial C-language description having a recursive function and recursive function call;

[0067]FIG. 16B, comprising FIGS. 16B1-16B5, shows HDL created by compiling the C-type program shown in FIG. 16A, illustrating a recursive function call to “MoveRing” utilizing addressable memory and a “stack_pointer” hardware register implemented in RTL Verilog;

[0068]FIG. 17A shows an initial C-language description having a function-call-by-pointer;

[0069]FIG. 17B, comprising FIGS. 17B1-17B2, shows HDL created by compiling the C-type program shown in FIG. 17A, illustrating the C-language pointer function implemented using a hardware register “state” assignment value corresponding to a first state of function “_main_f” in RTL Verilog;

[0070]FIG. 18A shows an initial C-language description having addressable variables;

[0071]FIG. 18B, comprising FIGS. 18B1-18B5, shows HDL created by compiling the C-type program shown in FIG. 18A, illustrating addressable memory implemented utilizing a hardware register file in RTL Verilog;

[0072]FIG. 19A shows an initial C-language description having multiple interdependent C-type functions;

[0073]FIG. 19B, comprising FIGS. 19B1-19B3, shows HDL created by compiling the C-type program shown in FIG. 19A, comprising multiple state machines implemented in RTL Verilog that operate in a data processing pipeline;

[0074]FIG. 19C is a block diagram of the data processing pipeline implemented by the RTL Verilog shown in FIG. 19B;

[0075]FIG. 20A shows an initial C-language description for a blinking light counter hardware design implemented utilizing a xilinx FPGA on an APS-X84 hardware board;

[0076]FIG. 20B, comprising FIGS. 20B1-20B2, shows HDL created by compiling the C-type program shown in FIG. 20A for a blinking light counter hardware design implemented utilizing a xilinx FPGA on an APS-X84 hardware board;

[0077]FIG. 21A shows an initial C-language description for a callable function;

[0078]FIG. 21B shows HDL created by compiling the C-type program shown in FIG. 21A, illustrating the use of a state machine to implement a cumulative adder function in RTL Verilog;

[0079]FIG. 21C shows HDL created by compiling the C-type program shown in FIG. 21A, illustrating the use of a state machine to implement the cumulative adder function in VHDL;

[0080]FIG. 22A shows an initial C-language description for reading a memory word located at the memory address referenced by the variable parameter “p” which has an ANSI C “pointer” type;

[0081]FIG. 22B shows HDL created by compiling the C-type program shown in FIG. 22A, illustrating reading a memory word located at the memory address referenced by the variable parameter “p”, which has an ANSI C “pointer” type, in RTL Verilog;

[0082]FIG. 22C shows a gate-level schematic comprised of clock enabled flip-flop hardware registers and control logic for reading 4-bit data located in external addressable memory at the location pointed by the 4-bit address, illustrating the compilation of the C-type program shown in FIG. 22A to a gate-level description;

[0083]FIG. 23A shows an initial C-language description for writing the content of the parameter variable “d” into a memory word located at the memory address referenced by the variable parameter “p” which has an ANSI C “pointer” type;

[0084]FIG. 23B shows HDL created by compiling the C-type program shown in FIG. 23A, which writes the content of the parameter variable “d” into a memory word located at the memory address referenced by the variable parameter “p”, which has an ANSI C “pointer” type, in RTL Verilog;

[0085]FIG. 23C shows a gate-level schematic comprised of clock enabled flip-flop hardware registers and control logic for writing 4-bit data into the external addressable memory at the addressable memory location pointed by the 4-bit address, illustrating the compilation of the C-type program shown in FIG. 23A to a gate-level description;

[0086]FIG. 24A shows an initial C-language description for reading a structure member by using pointer to structure;

[0087]FIG. 24B shows HDL created by compiling the C-type program shown in FIG. 24A for reading a structure member by using pointer to structure in RTL Verilog;

[0088]FIG. 24C shows a gate-level schematic comprised of clock enabled flip-flop hardware registers, control logic, and an adder for providing a constant offset to a given address for reading 4-bit data from the external addressable memory at the addressable memory location pointed by the 4-bit address plus offset, illustrating the compilation of the C-type program shown in FIG. 24A to a gate-level description;

[0089]FIG. 25A shows an initial C-language description for writing into a structure member using pointer to structure;

[0090]FIG. 25B shows HDL created by compiling the C-type program shown in FIG. 25A for writing into a structure member using pointer to structure in RTL Verilog;

[0091]FIG. 25C shows a gate-level schematic comprised of clock enabled flip-flop hardware registers, control logic, and an adder for providing a constant offset to a given address for writing 4-bit data into the external addressable memory at the addressable memory location pointed by the 4-bit address plus offset, illustrating the compilation of the C-type program shown in FIG. 25A to a gate-level description;

[0092]FIG. 26A shows an initial C-language description for reading a structure member from memory using a dot (“.”) operation;

[0093]FIG. 26B shows HDL created by compiling the C-type program shown in FIG. 26A for reading a structure member from memory using a dot (“.”) operation in RTL Verilog;

[0094]FIG. 26C shows a gate-level schematic comprised of clock enabled flip-flop hardware registers and control logic for reading 4-bit data from the external addressable memory at an address fixed at compile time on output wires “A0-1”, illustrating the compilation of the C-type program shown in FIG. 26A to a gate-level description;

[0095]FIG. 27A shows an initial C-language description for writing to a structure member located in memory;

[0096]FIG. 27B shows HDL created by compiling the C-type program shown in FIG. 27A for writing to a structure member located in memory in RTL Verilog; and

[0097]FIG. 27C shows a gate-level schematic comprised of clock enabled flip-flop hardware registers and control logic for writing 4-bit data into the external addressable memory at an address fixed at compile time on output wires “A0-1”, illustrating the compilation of the C-type program shown in FIG. 27A to a gate-level description.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0098] The computer aided hardware design tool in accordance with the various embodiments of the invention is executed on a computer 12, as shown in FIG. 1. The computer aided hardware design tool in accordance with one embodiment of the invention is preferably a 32-bit electronic computer aided design (ECAD) application compatible with a Microsoft Windows 95 or Microsoft NT 3.51 or later operating system available from Microsoft Corporation located in Redmond, Wash. The computer 12 comprises a minimum of 16 MB of random access memory (RAM) and preferably includes 32 MB of RAM. The computer 12 also comprises a hard disk drive having 40 MB of free storage space available.

[0099] In an alternative embodiment, the computer aided hardware design tool can be available by connecting to the web site of the supplier of the computer aided hardware design tool. The computer 12 is provided with an Internet connection, such as a modem, for connection to the web site of the supplier of the computer aided hardware design tool.

[0100] The computer aided hardware design tool can be ported to the web and executed on a web server. Therefore, the requirements for computer 12 would be reduced.

[0101] As shown in FIG. 1, means for displaying information preferably in the form of a monitor 14 connected to computer 12 is also provided. The monitor 14 can be a 640×480, 8-bit (256 colors) VGA monitor and is preferably an 800×600, 24-bit (16 million colors) SVGA monitor. The computer 12 is also preferably connected to a CD-ROM drive 16. As shown in FIG. 1, a keyboard 18 and a mouse 20 are provided for entry of an algorithmic representation for a hardware design in a high-level programming language, such as ANSI C, as well as mouse-driven navigation between menus displayed by the computer aided hardware design tool. The mouse 20 also enables persons utilizing the computer aided hardware design tool (referred to hereafter as “users”) to select simulation of a hardware design prior to implementation of a hardware design.

[0102] The computer aided hardware design tool in accordance with the invention enables a user to design hardware utilizing a high-level programming language, such as ANSI C. The fundamentals of ANSI C programming language are described, for example, in Kernighan, B. W., and Ritchie, D. M., The C Programming Language, Prentice Hall: New Jersey, 2d Ed., 1988. The computer aided hardware design tool of the invention then compiles the high-level program for the hardware design into a register transfer level (RTL) hardware description language (HDL) design which can be synthesized. The HDL may be, for example, Verilog, the fundamentals of which are described in Palnitkar, S., Verilog HDL: A Guide to Digital Design and Synthesis, SunSoft Press, Prentice Hall, 1996. For general information regarding compilers, see, for example, Aho, A. V., and Ullman, J. D., Principles of Compiler Design, Addison-Wesley Publishing Company, 2d Printing, March, 1978, and Hunter, R., The Design and Construction of Compilers, John Wiley & Sons, 1981.

[0103] The method in accordance with the invention for rendering a hardware design in a standard high-level programming language and converting that design into an actual hardware implementation will now be described. In accordance with one embodiment of the method of the invention, a user initially renders a preliminary hardware design as an algorithmic representation in a given standard high-level programming language. If the high-level programming language is not a C-type programming language, the high-level programming language preliminary hardware design is next translated from a preliminary hardware design rendered in the high-level programming language to a preliminary hardware design in a C-type programming language. Then, the C-type programming language preliminary hardware design is converted to a gate-level hardware representation which can be reduced to an actual hardware implementation, such as an FPGA or other programmable logic or an ASIC, using conventional physical design tools. This enables hardware designs rendered in virtually any standard high-level programming language to be implemented in hardware.

[0104] Considered in more detail, one embodiment of the method in accordance with the invention is shown in FIG. 2. A user can initially create an algorithmic representation corresponding to a preliminary hardware design using a given standard high-level programming language, as indicated by the step 30. Preferably, the high-level programming language is a programming language that can be translated into a C-type programming language, such as ANSI C, utilizing a conventional compilation program. Standard high-level programming languages that can be compiled to a C-type programming language utilizing conventional compilers include APL, Ada, Algol, B, Basic, Kernighan & Ritchie C, C++, CLOS, COBOL, Clu, Common Lisp, Coral, Dylan, Eiffel, Emacs Lisp, Forth, Fortran, IDL, Icon, Java, Jovial, Lisp, LOGO, ML, Modula, Oberon, Objective C, PL/I, PL/M, Pascal, Postscript, Prolog, Python, RTL, Rexx, SETL, Simula, Sather, Scheme, Smalltalk, Standard ML, TCL, and TRAC.

[0105] As indicated by the step 32 shown in FIG. 2, the high-level programming language algorithmic representation corresponding to the preliminary hardware design produced at step 30 is next translated into a C-type programming language preliminary hardware design. Translation results in a C-type programming language preliminary hardware design file, as indicated by the numeral 34 shown in FIG. 2. Preferably, the C-type programming language into which the high-level programming language preliminary hardware design is translated is ANSI C, such that an ANSI C preliminary hardware design file is produced at step 34.

[0106] Alternatively, the user can initially create the algorithmic representation corresponding to the preliminary hardware design in a C-type programming language, as indicated by the step 36 shown in FIG. 2. Preferably, the C-type programming language is ANSI C, such that an ANSI C preliminary hardware design file is produced at step 34. Therefore, the method in accordance with the invention enables a user to directly design hardware in a C-type programming language, preferably ANSI C programming language. This avoids the need at step 32 to translate from a different high-level programming language to a C-type programming language, for example, ANSI C.

[0107] As shown in FIG. 2, the C-type programming language preliminary hardware design file 34 can be run through a C compiler, as indicated by the step 38 shown in FIG. 2. This enables the user to verify or debug the C-type programming language preliminary hardware design.

[0108] Whether an algorithmic representation of a preliminary hardware design is initially created in a given standard high-level programming language translatable to a C-type programming language or created directly in the C-type programming language, such as ANSI C, the preliminary hardware design is compiled into a hardware description language (HDL) synthesizable design, as indicated by the step 40 shown in FIG. 2. For example, the C-type programming language preliminary hardware design can be compiled into to a Verilog synthesizable design to produce an RTL hardware design file 42, as shown in FIG. 2. The compilation of the C-type programming language preliminary hardware design into a synthesizable HDL design will be described in more detail below.

[0109] After the HDL design is produced, the method in accordance with the invention preferably comprises the step of simulating the HDL synthesizable design prior to synthesizing the HDL design, as indicated by the step 44 shown in FIG. 2. If the user desires to modify the preliminary hardware design in view of the simulation, the user renders a modified hardware design using either the given standard high-level programming language at step 30 or the C-type programming language, such as ANSI C, at step 36.

[0110] After an acceptable HDL design is obtained, the RTL hardware design file 42 representative of the HDL design is synthesized into a gate-level hardware representation using a conventional synthesis program to interpret the HDL design, as indicated by the step 46 shown in FIG. 2. This typically requires preselection of a particular hardware technology, such as an FPGA or ASIC, prior to the execution of the synthesis program. Synthesis programs are commercially available and do not constitute the invention per se. Therefore, the synthesis programs will not be described in detail.

[0111] In order to produce an actual hardware implementation, the method in accordance with the invention preferably further comprises the step of using conventional physical design tools to implement the gate-level hardware representation as an actual hardware implementation. These physical design tools include a place and route program. In the case of an FPGA, the physical design tools also include a hardware configuration system which processes the file produced by the place and route program and creates a bit stream to personalize the FPGA, as indicated by the step 48 shown in FIG. 2. In the case of an ASIC, the physical design tools include a place and route program for creating a file for patterning an integrated circuit mask for use in fabricating the ASIC, as indicated by the step 50 shown in FIG. 2. Physical design tools utilized to produce actual hardware implementations are commercially available and do not constitute the invention per se. Therefore, the physical design tools will not be described in detail. As shown in FIG. 2, an actual hardware implementation is produced, as indicated by the numeral 52.

[0112] A detailed description of the steps required for compiling a C-type programming language algorithmic representation for a preliminary hardware design into an HDL synthesizable design will now be provided by way of example. In the example, the C-type programming language is ANSI C and the HDL is preferably Verilog. However, it will be understood by persons skilled in the art that the principles of compiling a C-type programming language algorithmic representation for a preliminary hardware design into an HDL synthesizable design apply to other C-type programming languages besides ANSI C. For example, the C-type programming language may alternatively be any standard C-type programming language including ANSI C, B, C++, Java, Kernighan & Ritchie C, and Objective C. Moreover, the HDL synthesizable design into which the C-type programming language algorithmic representation for the preliminary hardware design is translated may be other than Verilog. For example, the HDL may alternatively be any standard HDL including VHDL, ABEL, CUPL, AHDL, MACHX, and PALASM.

[0113] The following describes compilation of the operations and functions that comprise ANSI C high-level programming language needed for hardware design into an exemplary HDL, namely, Verilog. As will be described later, the HDL may also be a different HDL, such as VHDL.

[0114] The method in accordance with the invention comprises mapping predetermined C-type programming language expressions to functionally equivalent HDL program language expressions. FIG. 3A illustrates a simple expression function in ANSI C programming language, and FIG. 3B represents the function shown in FIG. 3A compiled into RTL Verilog HAL.

[0115] In this regard, statements in ANSI C high-level programming language used to render hardware designs vary. For example, various ANSI C functions can be classified as “simple expression functions,” such as “func1” and “func2” shown in FIG. 3A. These functions have no side effects, do not require static memory access in HDL, and do not require a state machine in HDL to run. The determination of whether or not “simple expression functions” are present is performed by the code that appears in microfiche Appendix A in file OSYMBOLS.CPP at lines 5052-5232. Consequently, these functions can be compiled into simple RTL Verilog continuous assignments “result_func1” and “result_func2”, as shown in FIG. 3B. Compilation of the ANSI C expressions to functionally equivalent HDL expressions is performed by the code shown in the source code listing which appears in microfiche Appendix A in file GCODE.CPP at lines 5889-5990.

[0116] Furthermore, FIG. 3A illustrates C-type programming language expressions “a+b^ c<<3” and “(a^ b) & c”. In these expressions, “a”, “b”, and “c” are integer variables. FIG. 3B illustrates that these expressions are mapped into RTL Verilog expressions “((param_func1_a+param_func1_b)^ (param_func1_c^ <<16′d3))” and “((param_func2_a ^ param_func2_b) & param_func2_c)”, respectively. Also, integer variables “a”, “b”, and “c” in FIG. 3A are mapped onto wires “param_func1_a”, “param_func1_b”, and “param_func1_c” for ANSI C function “func1” and wires “param_func2_a”, “param_func2_b”, and “param_func2_c” for ANSI C function “func2”, respectively. This is because the ANSI C functions “func1” and “func2” are simple C-type functions which do not require implementation in RTL Verilog as state machines. The same mapping would occur if variables “a”, “b”, and “c” were defined as ANSI C floating point, pointer, enum, or union variables.

[0117] Additionally, FIGS. 3A and 3B illustrate assigning input/output as defined in the C-type program to specific wires in the HDL synthesizable design. The determination of whether or not C-type variables are to be mapped onto input/output wires of the generated RTL Verilog module is performed by the code shown in the source code listing which appears in microfiche Appendix A in file OSYMBOLS.CPP at lines 4802-5001. For example, parameters “a”, “b”, and “c” of the function “func1” shown in FIG. 3A are assigned to input wires, namely, “param_func1_a”, “param_func1_b”, and param_funcI_c”, respectively, of the module generated in RTL Verilog, as shown in FIG. 3B. Also, the result of the function “func1” (FIG. 3A) is assigned to an output wire “result func1” in RTL Verilog (FIG. 3B).

[0118]FIGS. 3A and 3B also illustrate a plurality of selected C-type functions that can execute simultaneously, which are compiled into a plurality of executable HDL program language expressions that operate in parallel. The determination of whether or not a plurality of simultaneously executable C-type functions is present is performed by the code shown in the source code listing which appears in microfiche Appendix A in file OSYMBOLS.CPP at lines 5052-5232. Compilation of the plurality of simultaneously executable C-type functions to a plurality of HDL expressions that operate in parallel is performed by the code shown in the source code listing which appears in microfiche Appendix A in file GCODE.CPP at lines 5889-5990.

[0119]FIGS. 4A and 4B also illustrate mapping predetermined C-type programming language expressions to functionally equivalent HDL program language expressions. FIGS. 4A and 4B show compilation from ANSI C (FIG. 4A) into RTL Verilog HDL (FIG. 4B) where no HDL state machine is required to implement the conversion of ANSI C functions. These ANSI C functions have no side effects, do not require static memory access in IHDL, and do not require a state machine in HDL to run. The advantage of utilizng state machines only when they are needed is that the compiled HDL design runs faster in hardware.

[0120] However, in contrast to the ANSI C functions shown in FIG. 3A, the ANSI C functions shown in FIG. 4A cannot be classified as “simple expression functions,” because they have data conversions or comprise at least one “if-then-else” statement. For example, “func1” shown in FIG. 4A contains a comparison operator that has different semantics in ANSI C than in RTL Verilog (i.e., utilizes temporary registers in Verilog).

[0121] Therefore, “func1” cannot be classified as a “simple expression function,” but it can be classified as a “function outside the HDL state machine.” These functions, such as “func1”, cannot be converted into one continuous assignment in HIDL but must instead be converted into multiple HDL statements within an “always” block. Note that FIGS. 4A and 4B also illustrate assigning input/output as defined in the C-type program to specific wires in the HDL synthesizable design, as described earlier in connection with FIGS. 3A and 3B.

[0122]FIGS. 5A and 5B illustrate compiling a C-type program control flow into an HDL state machine. FIG. 5A shows a simple “for” loop in ANSI C, and FIG. 5B shows compilation of the “for” loop into RTL Verilog HDL. The determination of whether or not a C-type program control flow that is to be converted to an HDL state machine is present is performed by the code shown in the source code listing which appears in microfiche Appendix A in file OSYMBOLS.CPP at lines 3735-4271.

[0123] As shown in FIG. SB, the “for” loop is implemented in RTL Verilog using a state machine. A state machine is utilized to implement the ANSI C program control flow, because the state machine provides the mechanism to execute the ANSI C operators in the required sequence. Compilation of the C-type program control flow into the HDL state machine is performed by the code shown in the source code listing which appears in microfiche Appendix A in file GCODE.CPP at lines 5930-6250.

[0124]FIGS. 5A and 5B also illustrate mapping non-addressable variables onto hardware registers formed in HDL as a result of compilation. The compilation is performed by the code shown in the source code listing which appears in microfiche Appendix A in file OSYMBOLS.CPP at lines 4802-5001. The non-addressable variables “n”, “i”, and “sum” employed in the ANSI C program shown in FIG. 5A are mapped onto hardware registers “_sum1_n”, “_2_sum_i”, and “_2_sum1_sum”, respectively, shown in FIG. 5B.

[0125] Additionally, FIGS. 5A and 5B illustrate mapping addressable variables onto addressable on-chip static memory formed in HDL as a result of compilation. The compilation is performed by the code shown in the source code listing which appears in microfiche Appendix A in file OSYMBOLS.CPP at lines 4802-5001. FIG. 5A shows that the ANSI C program includes an array “array” which is mapped onto addressable on-chip static memory having a starting memory address “_5_main_array”, as shown in FIG. 5B.

[0126]FIGS. 5A and 5B also illustrate assigning input/output as defined in the C-type program to specific wires in the HDL synthesizable design. The determination of whether or not C-type variables are to be mapped onto input/output wires of the generated RTL Verilog module is performed by the code which appears in microfiche Appendix A in file OSYMBOLS.CPP at lines 4802-5001. For example, parameter “n” of the function “sum1” shown in FIG. 5A is assigned to an input wire, namely, “param_sum1_n”, of the module generated in RTL Verilog, as shown in FIG. 5B. Also, the result of the function “sum1” (FIG. SA) is assigned to an output wire “result_sum1” in RTL Verilog (FIG. 5B).

[0127]FIGS. 6A and 6B illustrate compilation of standard ANSI C input/output (I/O) function calls into RTL Verilog HDL. The 10 function arguments (namely, “scanf and “printf” arguments) defined in the ANSI C program shown in FIG. 6A are assigned to specific wires in RTL Verilog, as shown in FIG. 6B.

[0128] The input function call “scanf” for reading data into ANSI C variables “a” and “b” shown in FIG. 6A is compiled into RTL Verilog for reading data from input wires, namely, “scanf_(—)0_(—)1_line_(—) 19_a” and “scanf _(—)0_(—)2_line_(—) 19_b”, into registers “ _(—)3_main_a” and “_(—)3_main_b”, respectively, as shown FIG. 6B. Accordingly, variables “a” and “b” in the ANSI C program (FIG. 6A) are mapped into registers “_(—)3_main_a” and _(—)3_main_b” in RTL Verilog (FIG. 6B). The output function call “printf” for writing the result of the ANSI C expression “a+b” shown in FIG. 6A is compiled into writing the result of the HDL expression “_3_main_a+_(—) 3_main_b” to an output wire, namely, “printf_(—)1_(—)1_line_(—)20” in RTL Verilog, as shown FIG. 6B.

[0129] As also shown in FIG. 6B, a Verilog statement “$write (“a+b=%d\n”, printf_1_(—)1_line_(—)20);” is preferably generated for the purpose of debugging the generated Verilog code. This statement is not used in connection with synthesis of the HDL design.

[0130]FIGS. 7A and 7B illustrate compiling multiple occurrences of a complicated C-type mathematical operation into a given HDL functional block that implements such an operation. The functional block is invoked on each occurrence by different states driven by the state machine.

[0131]FIG. 7A shows a C-type programming language expression “a/b+c/d”. This expression includes two divisions, namely, “a/b” and “c/d”. These divisions share the same divider unit implemented in RTL Verilog HDL. The divider unit is implemented in RTL Verilog, as follows. First, a divider module is defined, namely, “sdivmod16”. Second, the divider module “sdivmod16” is instantiated in the module “DivEx” comprising the state machine implemented in RTL Verilog. Third, the shared divider unit is driven employing the different states of the state machine, as shown in FIG. 7B. Since a single divider module is preferably utilized to reduce required hardware resources, the state machine is needed to sequentially multiplex arithmetic parameters to the inputs of the shared divider module in synchronization with the hardware clock. Compilation of the complicated C-type mathematical operation for division into a given HDL functional block for division that is invoked on the occurrence of different states of the state machine is performed by the code shown in the source code listing which appears in microfiche Appendix A in files GDIVMOD.CPP at lines 8487-9243, GEXPR.CPP at lines 7324-7646, and GFLOAT.CPP at lines 9244-9738. Based on the compilation of a division operation disclosed in FIGS. 7A and 7B, it should be apparent to persons skilled in the art how to handle other complicated arithmetic and logic operations, such as signed and unsigned integer multiplication, signed and unsigned integer remainder, variable-shift left shift, variable-shift right shift with or without sign extension, etc.

[0132] ANSI C variables “a”, “b”, “c”, and “d” shown in FIG. 7A are defined as integer variables. These variables are mapped onto wires “param_func_a”, “param_func_b”, “param_func_c”, and “param_func_d” of the RTL Verilog module, respectively. The same mapping would occur if variables “a”, “b”, “c”, and “d” were defined as ANSI C floating point, pointer, enum, or union variables.

[0133] ANSI C does not support the concept of“pipelining.” However, it has been determined that ANSI C constructs can be utilized to define a hardware data processing pipeline.

[0134] As shown in FIGS. 8A and 8B, the method in accordance with the invention may also comprise compiling a plurality of interdependent C-type functions into a plurality of executable HDL program language expressions that operate either simultaneously or sequentially in a data processing pipeline. C-type functions are interdependent when the input of one of the functions is dependent upon the output of another function. FIGS. 8A and 8B illustrate compilation of three simple ANSI C functions (FIG. 8A) into a data processing pipeline implemented in RTL Verilog HDL (FIG. 8B).

[0135] As shown in FIG. 8C, the data processing pipeline consists of three stages. The first stage of the pipeline corresponds to the ANSI C function “pipeline_stage_(—)1”. This first stage is an adder which adds the value “1” to the value from the input wire “_data_in”, which corresponds to the ANSI C variable “data_in”, and writes the sum into the hardware register “out1”, which corresponds to the ANSI C variable “out1”. The second stage of the pipeline corresponds to the ANSI C function “pipeline_stage_(—)2” which uses the output “_out1” and adds that value to itself and writes the sum into the hardware register “_out2” which corresponds to the ANSI C variable “out2”. The third stage of the pipeline corresponds to the ANSI C function “pipeline_stage_(—)3” which uses the output “_out2” of the second stage and performs an “XOR” logic function with the value “1234” and writes the result onto the output wire “_data_out” which corresponds to the ANSI C variable “data_out”. FIG. 8B illustrates that the three stages of the data processing pipeline are implemented by three “always” blocks in RTL Verilog, which operate simultaneously. Alternatively, the stages of the data processing pipeline implemented in RTL Verilog may be operated sequentially depending upon usage of input signals “run_pipeline_(—)1”, “run_pipeline_(—)2”, and “run_pipeline_(—)3”. The compilation is performed by the code shown in the source code listing which appears in microfiche Appendix A in file OSYMBOLS.CPP at lines 4896-4950.

[0136] Variable “data_in” shown in the ANSI C program (FIG. 8A) has “external scope,” as defined in the ANSI C standard. The address of “data_in” is not used by any C-type function or for C-type initialization of any variable. Furthermore, “data_in” is never used as an 1-value. That is, “data_in” is used in the ANSI C program as a readable variable, but it is not used as a writable variable. Also, “data_in” is not initialized in the ANSI C program.

[0137] Because “data_in” has these attributes, it is mapped onto an input wire “_data_in” of an HDL module, as shown in FIG. 8B. The input wire is utilized as an input wire of a hardware pipeline stage implemented in RTL Verilog (FIG. 8B).

[0138] Variable “data_out” shown in the ANSI C program (FIG. 8A) also has “external scope.“The address of ”data_out” is not used by any C-type function or for C-type initialization of any variable. Furthermore, “data_out” is used only as an 1-value. That is, “data_out” is used in the ANSI C program as a writable variable, but it is not used as a readable variable. Also, “data_out” is not initialized in the ANSI C program.

[0139] Since “data_out” has the above attributes, it is mapped onto an output wire “_data_out” of the HDL module, as shown in FIG. 8B. The output wire is utilized as an output wire of the hardware pipeline stage implemented in RTL Verilog (FIG. 8B).

[0140]FIGS. 8A and 8B illustrate a simple pipeline. That is, the ANSI C program shown in FIG. 8A is compiled into RTL Verilog without the need for an HDL state machine.

[0141]FIGS. 9A and 9B illustrate floating point arithmetic and double precision floating point arithmetic in ANSI C (FIG. 9A) and compilation into RTL Verilog HDL (FIG. 9B). This demonstrates that the method in accordance with the invention can convert floating point operations into a state-machine-based protocol of transactions to an external floating point arithmetic unit (FPU) preferably implemented in adjunct hardware. Since FPUs are commercially available, definition of an FPU in the RTL Verilog generated during compilation of the ANSI C arithmetic operations is not required. Instead, all that is needed is the assignment of output and input wires to such an FPU, which defines an interface between the RTL Verilog generated design and the FPU.

[0142] As shown in FIGS. 9A and 9B, each of the ANSI C arithmetic operations is compiled into a sequence of states of the state machine in RTL Verilog. During a first state, the parameters needed for the floating point operations are written to output wires assigned in RTL Verilog, which are read by the external floating point arithmetic unit. During a second state, the state machine awaits completion of performance of the arithmetic operations by the arithmetic unit. During a third state, the results of the floating point arithmetic operations are written by the arithmetic unit onto the input wires defined in RTL Verilog and read.

[0143]FIGS. 9A and 9B show compilation from ANSI C into RTL Verilog for subtraction from zero (unary −), addition, multiplication, subtraction, division, and conversion operations, which involve floating point arithmetic. Therefore, in view of the methodology shown in FIGS. 7A, 7B, 9A, and 9B, it will be apparent to persons skilled in the art that all complicated integer and floating point operations can be compiled into RTL Verilog.

[0144]FIGS. 10A and 10B illustrate compilation of descriptions with structures, including structure assignment, structure function parameters, and structure function return values, which are commonly employed to implement algorithms, in ANSI C (FIG. IOA) and following compilation into RTL Verilog HDL (FIG. 10B). FIG. 10A shows the addition of two complex numbers implemented as ANSI C structures. The expression “z”=add (x, add (x,y))” contains the structure assignment to structure “z”, and structures “x” and “y” are employed as structure function parameters of the function “add”. Function “add” returns a structure return value which is equal to structure “c”. FIG. 10A also illustrates structure members “real” and “image”, which are employed both as 1-value (value on the left-hand side of the assignment operation) and revalue (value on the right-hand side of the assignment operation). FIG. 10B illustrates that structure function parameters and structure function return values are implemented utilizing wide (i.e., 32-bit) hardware registers which can store the entire structure, including structure members (i.e., “real” and “image”). Temporary wide (i.e., 32-bit) hardware registers are also utilized for the structure assignment translation to read the r-value structure from external memory and to write the 1-value structure to the external memory. Compilation of structure assignment and structure return values and assignment of structure function parameters is performed by the code shown in the source code listing which appears in microfiche Appendix A in file GEXPR.CPP at lines 8101-8255. It will be understood by persons skilled in the art that the same compilation process can be applied to C-type programming language structure assignment, structure function parameters, and structure function return values in C-type programs which do not require implementation of a state machine in RTL Verilog.

[0145]FIGS. 11A and 11B illustrate compiling C-type pointers and pointer indirection into an HDL state-machine-based memory access protocol. FIG. 11A shows C-type pointers, such as local variable “p”, return value of function “FindNode”, global variable “pTree”, and structure members “pLeft” and “pRight”. On the one hand, local variable “p” is not addressable, that is, its address is never read. Therefore, this non-addressable variable is mapped onto a hardware register formed in RTL Verilog HDL, namely, “_(—)7_FindNode_p”, as shown in FIG. 11B. On the other hand, variable “pTree” is addressable, that is, its address is read in the expression “p=&pTree;”, as shown in FIG. 11A. Therefore, this addressable variable is mapped onto a memory location identified by the address “_Tree” in external addressable hardware memory, as shown in FIG. 11B. Compilation of C-type pointers and pointer indirection into an HDL state-machine-based memory access protocol is performed by the code shown in the source code listing which appears in microfiche Appendix A in files GRW.CPP at lines 10040-10438 and GEXPR.CPP at lines 6724-6750, 7252-7282, and 8101-8255.

[0146] Also, “Nodes” is an addressable variable because it is a C-type programming language array. Therefore, this addressable variable is mapped onto a memory location identified by the address “_Nodes” in external addressable hardware memory, as shown in FIG. 11B.

[0147] FIG. I lA also illustrates a “while” loop, “if-then-else” statement, “return”, and function call (i.e., “FindNode” is called by the function “FindValue”) in ANSI C programming language, and FIG. 11B illustrates implementation of these as a state machine in RTL Verilog. FIGS. 11A and 11B also provide another illustration of the handling of C-type programming language structures, including translation of the operation “−>” (i.e., structure member dereferencing by pointer).

[0148] The method of the invention may also comprise compiling a callable C-type function into a functionally equivalent HDL program language expression that is executed synchronously on the occurrence of an external event. FIGS. 12A and 12B illustrate a simple case of synchronous event detection in the case where the HDL expression does not require a state machine. The C-type function “on_event” represents any executable C-type function, which is called for execution by another C-type function, for example, “main.” This call is converted into RTL Verilog HDL that is executable on the occurrence of an external event, such as assertion of a signal on an input wire. The determination of whether or not a callable C-type function is present is performed by the code shown in the source code listing which appears in microfiche Appendix A in file OSYMBOLS.CPP at lines 5052-5232. Thus, the C-type function “on_event” (FIG. 12A) is compiled into RTL Verilog that is executed when signal “run_on_event” is asserted true (FIG. 12B). Compilation of the callable C-type function into a functionally equivalent HDL program language expression which is executed synchronously on the occurrence of an external event is performed by the code shown in the source code listing which appears in microfiche Appendix A in file GCODE.CPP at lines 5889-5990. Event detection in this implementation is synchronous, that is, the event is detected only on a positive edge of a clock signal. It will be understood by persons skilled in the art that the same compilation process can be applied to a callable C-type function which requires implementation of a state machine in RTL Verilog in the case in which the state machine is executed synchronously on the occurrence of an external event. The following example will illustrate asynchronous event detection.

[0149]FIGS. 13A and 13B illustrate compiling a callable C-type function into a functionally equivalent HDL program language expression that is executed asynchronously after the occurrence of an external event. FIGS. 13A and 13B illustrate a simple case of asynchronous event detection in the case where the HDL expression does not require a state machine. The determination of whether or not a callable C-type function is present is performed by the code shown in the source code listing which appears in microfiche Appendix A in file OSYMBOLS.CPP at lines 5052-5232.

[0150] As in the case of FIG. 12A, the C-type function “on_event” shown in FIG. 13A again represents any executable C-type function which is called for execution by another C-type function, for example, “main.” However, as shown in FIG. 13B, this call is converted into RTL Verilog HDL that is executable following occurrence of an external event, such as transition of a signal on an input wire. That is, the pragma causes the C-type function “on_event” (FIG. 13A) to be compiled into RTL Verilog which is executed when signal “run_on_event” transitions from false to true (FIG. 13B). This occurs asynchronously relative to the occurrence of the positive edge of a clock signal (“posedge clock”). Compilation of the callable C-type function into a functionally equivalent HDL program language expression which is executed asynchronously on the occurrence of an external event is performed by the code shown in the source code listing which appears in microfiche Appendix A in file GCODE.CPP at lines 5889-5990. Note that asynchronous event processing must handle timing constraints that do not occur in the synchronous event implementation shown in FIGS. 12A and 12B.

[0151] It will be understood by persons skilled in the art that a similar compilation process can be applied to a callable C-type function that requires implementation of a state machine in RTL Verilog HDL. In the case in which the state machine is executed asynchronously with respect to the occurrence of an external event, instantiation of a flip-flop is required in RTL Verilog to store the occurrence of the event. If this flip-flop is set, the state machine runs on the next-occurring positive edge of a clock signal.

[0152]FIGS. 14A and 14B illustrate parallel processing of two complex C-type functions and two state machines running simultaneously. These functions (“funcd” and “func2”) do not interfere with each other, which means they: 1) do not call each other; 2) do not share external or on-chip static memory; 3) do not share an HDL functional block that performs a complicated mathematical operation; and 4) do not write into the same hardware register. Because of this fact, these functions can be performed simultaneously. External logic can safely assert signals “run_func1” and “run_func2” at any time independently of each other, as shown in FIG. 14B. Compilation of the complex C-type functions that can execute simultaneously into a plurality of HDL state machines that operate in parallel is performed by the code shown in the source code listing which appears in microfiche Appendix A in file GCODE.CPP at lines 5615-6251. Since these functions require state machines to implement them, their execution is synchronous with the positive edge of a clock signal.

[0153]FIGS. 15A and 15B illustrate compilation of ANSI C variable argument functions and variable argument function calls into RTL Verilog HDL. As shown in FIG. 15A, the ANSI C variable argument function “average” is called from another ANSI C function “main” . In order to convert the variable argument function call “average” to RTL Verilog, a temporary parameter storage location in addressable memory is utilized. This temporary storage location resides immediately after the location of the last fixed parameter, namely, “average-first”, of the variable argument function “average”, as shown in FIG. 15B. When function “main” calls function “average” , function “main” sets the parameters for function “average” by writing values for those parameters into the addressable memory at the temporary parameter storage location.

[0154] The method in accordance with the invention also supports the use of ANSI C recursive function calls. The C-type program is parsed to determine whether or not a direct or indirect recursive function call is present. That is, a global analysis of the C-type program is performed to determine which functions are recursive. Any identifiable direct or indirect recursive function call is compiled into an HDL state machine which has an interface to a stack implemented utilizing either external or internal memory or, alternatively, an array of hardware registers. The generated RTL Verilog module has a stack pointer implemented utilizing a hardware register employed to store and restore local variables of the recursive function and other recursive function information.

[0155]FIGS. 16A and 16B illustrate compilation of an ANSI C recursive function and recursive function call into RTL Verilog HDL. As shown in FIG. 16A, the ANSI C recursive function “MoveRing” is called from itself and from another ANSI C function “Hanoi”. In order to translate the recursive function call to “MoveRing” into RTL Verilog:

[0156] 1. A designated region of addressable memory at the location “recursion_stack” is established in RTL Verilog, as shown in FIG. 16B.

[0157] 2. A designated hardware register, namely “stack_pointer”is defined in RTL Verilog, as also shown in FIG. 16B.

[0158] 3. Before the recursive function “MoveRing” calls itself (i.e., the recursive function “MoveRing”), recursive function “MoveRing” saves its local context into the established stack which consists of the designated region of the addressable memory at the location “recursion_stack” and the designated hardware register, namely, “stack_pointer” . The recursive function “MoveRing” local context contains recursive function “MoveRing” local variable and parameter registers, namnely, “_MoveRing_nRings”, “MoveRing_Tower1”, “_MoveRing_Tower2”, “MoveRing_Tower3”, and the recursive function “MoveRing” return state register, namely, “return_state_MoveRing”.

[0159] 4. After the recursive function “MoveRing” call, the recursive function “MoveRing” restores its local context, as shown in FIG. 16B.

[0160] By storing and restoring its local context before and after the recursive call, respectively, the recursive function “MoveRing” avoids losing its local context. Before the recursive function calls itself, it saves the local context on the memory stack (an addressable memory). After executing the function, the recursive function restores its local context.

[0161]FIGS. 17A and 17B illustrate compilation of an ANSI C function-call-by-pointer into RTL Verilog HDL. As shown in FIG. 17A, the ANSI C functions “f1” and “2” are called from the ANSI C function “main” using a pointer variable “f”. Depending upon the value of parameter “n” of the ANSI C function “main” , either pointer-to-function “f1” or pointer-to-function “f2” is assigned to the pointer variable “f”. Then, the ANSI C function “main” calls one of “f1” or “f2” using the pointer variable “f”. This ANSI C function-call-by-pointer is translated into RTL Verilog by assigning the hardware register “state” a value corresponding to the first state of the function, namely, “_main_f”, as shown in FIG. 177B. The assigned value becomes the current state of the generated state machine. Depending upon the value of the “_main_n” hardware register in RTL Verilog, the pointer-to-function hardware register “_main_f” is assigned to either state “_f1” or to state “_f2” in RTL Verilog, which correspond to ANSI C functions “f1” and “f2”, respectively.

[0162]FIGS. 18A and 18B illustrate mapping addressable variables defined in C-type programming language onto an addressable array of hardware registers formed in HDL. Specifically, “array” is an addressable variable, because it is a C-type programming language array, as shown in FIG. 18A. Therefore, this ANSI C array is mapped onto addressable memory implemented as an addressable array of hardware registers, namely, “memory” in RTL Verilog HDL, as shown in FIG. 18B. The compilation is performed by the code shown in the source code listing which appears in microfiche Appendix A in file OSYMBOLS.CPP at lines 4802-5001. The starting address of the ANSI C “array” in the “memory” array in RTL Verilog shown in FIG. 18B is “offset_main_(—)3_main_array”.

[0163] The method in accordance with the invention may also comprise compiling a plurality of interdependent C-type functions into a plurality of HDL state machines that operate in a data processing pipeline. FIGS. 19A and 19B illustrate compilation of three ANSI C functions (FIG. 19A) into a data processing pipeline implemented in RTL Verilog HDL (FIG. 19B). In contrast to the three-stage data processing pipeline shown in FIG. 8C, the three-stage data processing pipeline shown in FIG. 19C comprises a separate state machine to implement each of the three stages of the data processing pipeline in RTL Verilog. Otherwise, the configuration of the data processing pipeline shown in FIG. 19C is similar to the configuration of the data processing pipeline shown in FIG. 8C. Although the implementation of the data processing pipeline in RTL Verilog shown in FIG. 199B includes a state machine for each stage, other ANSI C functions do not require the implementation of state machines, as in the case of the data processing pipeline shown in FIG. 8B. Alternatively, the data processing pipeline may comprise a combination of simple HDL functional blocks and state machines. The compilation is performed by the code shown in the source code listing which appears in microfiche Appendix A in file OSYMOLS.CPP at lines 4896-4950.

[0164]FIGS. 20A and 20B illustrate that a hardware design originally rendered in ANSI C programming language may be implemented in actual hardware. The target hardware was a Xillinx FPGA on an APS-X84 hardware board. The board was installed in a slot in a computer. The result was to implement a counter whose operation is evidenced by a blinking LCD on the board. The frequency of blinking is determined by the on-board clock rate and the user-specified terminal count. FIG. 20A illustrates the hardware design rendered in ANSI C programming language, and FIG. 20B shows the Verilog code after compilation.

[0165]FIG. 20B also shows configuration of an interface in the HDL synthesizable design for the gate-level hardware representation. That is, an additional interface Verilog module with wire assignments is needed to map the hardware I/O pins of the target hardware (APS-X84 FPGA) to the computer bus. This is shown in FIG. 20B after the comment “// APSX84.v - Verilog wrapper module which instantiates module Light.v.”.

[0166] The HDL design may be simulated prior to and/or after the wire assignments are mapped to the I/O pins. For example, one of various simulation programs commercially available from Wellspring Solutions, Cadence Design Systems, Mentor Graphics Corporation, Synopsis, Viewlogic Systems, or Veri Best, Inc. may be used for simulation of the HDL design.

[0167] The hardware implementation may be performed using physical design tools to implement the gate-level representation produced by synthesizing the Verilog code using one of various synthesis programs commercially available from Synplicity, Synopsys, or Exemplar Logic. In this example, the physical design tool that was used is commercially available from Xilinx.

[0168] The foregoing describes compilation of a hardware design rendered in ANSI C high-level programming language into an HDL synthesizable design in RTL Verilog HDL. The following example illustrates the compilation of a hardware design rendered in ANSI C into an HDL synthesizable design in both Verilog and VHDL. Therefore, the computer aided hardware design tool in accordance with the invention can provide compilation of a hardware design rendered in ANSI C high-level programming language into any of various AHDLs.

[0169] FIGS. 21A-21C illustrate compilation of a hardware design from a high-level programming language to several HDLs commonly employed for hardware design. FIG. 21A shows a hardware design for a callable function rendered in ANSI C high-level programming language. FIG. 21A comprises the ANSI C text for the hardware design. FIG. 21B shows the same hardware design compiled into RTL Verilog HDL. FIG. 21B comprises the Verilog text for the hardware design. FIG. 21C shows the same hardware design compiled into another commercially available HDL, namely, VHDL. FIG. 21C comprises the VHDL text for the hardware design.

[0170] In accordance with one aspect of the invention, ANSI C pointer and structure operations are translated into transactions to external or on-chip static memory in a gate-level hardware representation. The known prior art does not process ANSI C pointers or structures and therefore disallows the use of pointers and structures in rendering a hardware design.

[0171] In accordance with a preferred embodiment of the invention, the ANSI C pointer operations are compiled into HDL that is synthesized to a gate-level hardware representation. FIG. 22A illustrates an ANSI C progranmning language description for reading a memory word located at the memory address referenced by the variable paramneter “p” which has an ANSI C “pointer” type. FIG. 22B illustrates compilation of the ANSI C pointer operation “*” into RTL Verilog HDL that can be synthesized into a gate-level hardware design file, or netlist. FIG. 22C is a gate-level schematic diagram created from the netlist. FIG. 22C shows clock-enabled flip-flop hardware registers and control logic for reading 4-bit data located in external addressable memory at the location pointed by a 4-bit address on wires “PARAM_READ_P0-3”, which illustrates the compilation of the C-type program to a gate-level hardware description. The external or on-chip memory is addressed by the address stored on wires “A0-3” at the Q outputs of the flip-flops shown in the lower portion of FIG. 22C. The memory returns the addressed data on wires “D0-3”. The addressed data are clocked to the Q outputs of the flip-flops shown in the top portion of FIG. 22C onto wires “RESULT_READ0-3”. Although FIGS. 22A-22C show a 4-bit-wide variable, the variable may have any desired width, such as a 16- or 32-bit width.

[0172]FIG. 23A illustrates an ANSI C programming language description for writing the content of the parameter variable “d” into a memory word located at the memory address referenced by the variable parameter “p” which has an ANSI C “pointer” type. FIG. 23B illustrates compilation of the ANSI C 4-bit-wide variable “d” into RTL Verilog HDL that can be synthesized into a netlist. FIG. 23C is a gate-level schematic diagram created from the netlist. FIG. 23C shows clock-enabled flip-flop hardware registers and control logic for writing 4-bit data to external addressable memory at the location pointed by a 4-bit address on wires “PARAM_WRITE_P0-3”. The external memory is addressed by the values stored on wires “A0-3” at the Q outputs of the flip-flops shown in the top portion of FIG. 23C. The data to be stored are clocked from the wires “PARAM_WRITE_D0-3” to the D inputs of the flip-flops shown in the lower portion of FIG. 23C onto wires “D0-3”. Although FIGS. 23A-23C show a 4-bit-wide variable, the variable may have any desired width, such as a 16- or 32-bit width.

[0173] Also in accordance with a preferred embodiment of the invention, ANSI C structure operations are compiled into HDL that is synthesized to a gate-level hardware representation. FIG. 24A illustrates an ANSI C programming language description for reading a memory word located at the memory address referenced by the variable parameter “p” which has an ANSI C “pointer-to-structure” type and a fixed offset corresponding to the structure member “b”. FIG. 24B illustrates compilation of the ANSI C structure operation “−>” into RTL Verilog HDL that can be synthesized into a gate-level hardware design file, or netlist. FIG. 24C is a gate-level schematic diagram created from the netlist. FIG. 24C shows clock-enabled flip-flop hardware registers, control logic, and an adder for providing a constant offset to a given address for reading 4-bit data located in external addressable memory at the location pointed by a 4-bit address on wires “PARAM_READ_MEMBER_B_P0-3” plus the offset provided by the adder, which illustrates the compilation of the C-type program to a gate-level hardware description. The external or on-chip memory is addressed by the address stored on wires “A0-3” at the Q outputs of the flip-flops shown in the upper portion of FIG. 24C. The memory returns the addressed data on wires “D0-3”. The addressed data are clocked to the Q outputs of the flip-flops shown in the lower portion of FIG. 24C onto wires “RESULT_READ_MEMBER_B0-3”. Although FIGS. 24A-24C show a 4-bit-wide variable, the variable may have any desired width, such as a 16- or 32-bit width.

[0174]FIG. 25A illustrates an ANSI C programming language description for writing the content of the parameter variable “n” into a memory word located at the memory address referenced by the variable parameter “p” which has an ANSI C “pointer-to-structure” type and a fixed offset corresponding to the structure member “b”. FIG. 25B illustrates compilation of the ANSI C structure operation “−>” into RTL Verilog HDL that can be synthesized into a netlist. FIG. 25C is a gate-level schematic diagram created from the netlist. FIG. 25C shows clock-enabled flip-flop hardware registers, control logic, and an adder for providing a constant offset to a given address for writing 4-bit data to external addressable memory at the location pointed by a 4-bit address on wires “PARAM_WRITE_MEMBER_B_P0-3” plus the offset provided by the adder. The external memory is addressed by the values stored on wires “A0-3” at the Q outputs of the flip-flops shown in the top portion of FIG. 25C. The data to be stored are clocked from the wires “PARAM_WRITE_MEMBER_B_N0-3” to the D inputs of the flip-flops shown in the lower portion of FIG. 25C onto wires “DO-3”. Although FIGS. 25A-25C show a 4-bit-wide variable, the variable may have any desired width, such as a 16- or 32-bit width.

[0175]FIG. 26A illustrates an ANSI C programming language description for reading a memory word located at the memory address referenced by the fixed address determined at compile time of the “b” member of structure “s”. FIG. 26B illustrates compilation of the ANSI C structure operation “.” into RTL Verilog HDL that can be synthesized into a gate-level hardware design file, or netlist. FIG. 26C is a gate-level schematic diagram created from the netlist. FIG. 26C shows clock-enabled flip-flop hardware registers and control logic for reading 4-bit data located in external addressable memory at the location pointed by a fixed address “2”, which illustrates the compilation of the C-type program to a gate-level hardware description. The external or on-chip memory is addressed by the address stored on wires “A0-1” at the Q outputs of the flip-flops shown in the middle portion of FIG. 26C. The memory returns the addressed data on wires “D0-3”. The addressed data are clocked to the Q outputs of the flip-flops shown in the lower portion of FIG. 26C onto wires “RESULT_READ_MEMBER_B0-3”. Although FIGS. 26A-26C show a 4-bit-wide variable, the variable may have any desired width, such as a 16- or 32-bit width.

[0176]FIG. 27A illustrates an ANSI C programming language description for writing the content of the parameter variable “n” into a memory word located at the memory address referenced by the fixed address determined at compile time of the “b” member of structure “s”. FIG. 27B illustrates compilation of the ANSI C structure operation “.” into RTL Verilog HDL that can be synthesized into a netlist. FIG. 27C is a gate-level schematic diagram created from the netlist FIG. 27C shows clock-enabled flip-flop hardware registers and control logic for writing 4-bit data to external addressable memory at the location pointed by a fixed address “2”. The external memory is addressed by the values stored on wires “A0-1” at the Q outputs of the flip-flops shown in the middle portion of FIG. 27C. The data to be stored are clocked from the wires “PARAM_WRITE_MEMBER_B_N0-3” to the D inputs of the flip-flops shown in the lower portion of FIG. 27C onto wires “D0-3”. Although FIGS. 27A-27C show a 4-bit-wide variable, the variable may have any desired width, such as a 16- or 32-bit width.

[0177] According to one modification, ANSI C pointer and structure operations for a read operation may be directly implemented in a gate-level hardware description by configuring a series of flip-flops in hardware corresponding to the number of bits of memory address and another series of flip-flops corresponding in number to the number of bits of data to be read, and by providing control logic that enables data to be read from addressable external or on-chip hardware memory to output wires. ANSI C pointer and structure operations for a write operation may also be directly implemented in a gate-level hardware description by configuring a series of flip-flops in hardware corresponding to the number of bits of memory address and another series of flip-flops corresponding in number to the number of bits of data to be written, and by providing control logic that enables data to be written from addressable external or on-chip hardware memory to input wires. For example, a generalized circuit configuration may be defined in a library, and the number m of bits of data and the number n of bits of address would be directly derived from the ANSI C pointer to define the schematic for the circuit. Therefore, ANSI C pointer and structure operations may be automatically converted by a parameterizable library look-up using values for m and n to gate-level hardware descriptions similar to the schematics shown in FIGS. 22C and 23C for pointer operations and in FIGS. 24C, 25C, 26C, and 27C for structure operations, respectively.

[0178] In summary, prior art computer aided hardware design tools generate so many unhandled exceptions and language restrictions when presented with typical high-level language programs (e.g., a C-type program) that it renders such tools virtually useless for practical hardware design. Therefore, persons using such tools are required to read manuals and attempt to create work-arounds for portions of the high-level programming language that are not implemented. In contrast, a salient feature of the system in accordance with the invention is that almost any ANSI C (or high-level programming language translatable to a C-type programming language) can be compiled, thereby obviating the need for the user to read manuals and attempt to create work-arounds for portions of the high-level programming language that are not implemented. Existing programs in a high-level programming language can typically be fed directly into the system in accordance with the invention without any error messages being generated.

[0179] Hardware generated using prior art computer aided hardware design tools is typically based on simple line-by-line, table-driven translation and as such does not contain the necessary widely scoped optimizations that produce practical and useful hardware designs for most applications. The system in accordance with the invention supports all functions of the high-level programming language in which the hardware design is rendered at compile time and re-uses HDL functional blocks for hardware design efficiency.

[0180] Design output of the prior art computer aided hardware design tool can be in so-called “behavioral HDL,” which in many cases cannot be synthesized by existing synthesis programs into a gate-level representation of the hardware. The system in accordance with the invention generates register transfer level HDL that can always be synthesized.

[0181] Prior art computer aided hardware design tools attempt to generate designs that only apply to a single manufacturer hardware family, such as the creation of an XNF file for the Xilinx XC4000 FPGA family. In contrast, the system of the invention converts to a synthesizable HDL which can be synthesized by standard synthesis programs for implementation on hardware platforms of any one of a number of manufacturers, including Altera, Xilinx, Actel, Texas Instruments, LSI Logic, VLSI Technology, Lucent Technologies, NEC, Hitachi, Toshiba, Fujitsu, and others.

[0182] Finally, the language employed by prior art computer aided hardware design tools has added and limited so many constructs that it is difficult to consider the employed language as the high-level language it purports to be. That is, the resultant language is more like a new specialized HDL. In contrast, the system in accordance with the invention enables the user to truly use a high-level programming language, such as ANSI C, to design hardware.

[0183] The table below summarizes which prior art attempts described earlier have which shortcomings and shows the advantageous features of the system in accordance with the invention. The table clearly evidences that the system of the invention is a unique contribution to the state-of-the-art. Comparison of System to Prior Art Feature Invention TMCC JRS NLC Handel-C XC 1. Substantially Yes No No No No No full ANSI C 2. Logic design Yes No No No Yes Yes optimized 3. Design Yes Yes No Yes Yes Yes synthesizable 4. Targets general Yes No Yes No No No HDL 5. Is high-level Yes Yes Yes Yes No No programming language (not specialized new HDL)

[0184] It will be understood and appreciated that the embodiments of the present invention described above are susceptible to various modifications, changes, and adaptations. For example, the computer aided hardware design tool in accordance with the invention can also convert other high-level programming languages than those that are specifically identified to a synthesizable hardware description language. Also, although the preferred embodiments have been described for a personal computer (PC) operating system platform, it will be appreciated that the computer aided design tool in accordance with the invention can alternatively be adapted for execution on any other type of operating system platform, such as a UNIX operating system platform. These contemplated alternative embodiments and other modifications, changes, and adaptations are intended to be comprehended within the meaning and range of equivalents of the appended claims. 

What is claimed is:
 1. A method for converting a C-type language program to a hardware design, comprising the steps of: creating an algorithmic representation in a given C-type programming language corresponding to a preliminary hardware design; and compiling the C-type programming language preliminary hardware design into a hardware description language (HDL) synthesizable design.
 2. The method of claim 1 , further comprising the step of synthesizing the HDL design into a gate-level hardware representation using a synthesis program to interpret the HDL design.
 3. The method of claim 2 , further comprising the step of using physical design tools to implement the gate-level representation as an actual hardware implementation.
 4. The method of claim 1 wherein the C-type programming language is selected from among the group of C-type programming languages consisting of ANSI C, B, C++, Java, Kernighan & Ritchie C, and Objective C.
 5. The method of claim 1 wherein the hardware description language is selected from among the group of hardware description languages consisting of Verilog, VHDL, ABEL, CUPL, AHDL, MACHX, and PALASM.
 6. The method of claim 1 , further comprising the step of simulating the HDL synthesizable design.
 7. The method of claim 1 wherein the step of compiling comprises the steps of: mapping predetermined C-type programming language expressions to functionally equivalent HDL program language expressions; and assigning input/output as defined in the C-type program to specific wires in the HDL synthesizable design; and further comprising the step of configuring in the HDL synthesizable design an interface for the gate-level hardware representation.
 8. The method of claim 7 wherein a plurality of selected C-type functions that can execute simultaneously are compiled into a plurality of executable HDL program language expressions that operate in parallel.
 9. The method of claim 7 wherein a plurality of interdependent C-type functions are compiled into a plurality of executable HDL program language expressions that operate one of simultaneously and sequentially in a data processing pipeline.
 10. The method of claim 7 wherein a callable C-type function is compiled into an executable HDL program language expression that is executed one of synchronously and asynchronously on the occurrence of an external event.
 11. The method of claim 7 wherein the C-type programming language expressions include at least one of integer, floating point, pointer, enum, struct, and union variables.
 12. The method of claim 7 , further comprising the step of compiling C-type programming language structure assignment, structure function parameters, and structure function return values into HDL synthesizable expressions.
 13. The method of claim 1 wherein the step of compiling comprises the steps of: compiling a C-type program control flow into an HDL state machine; and assigning input/output as defined in the C-type program to specific wires in the HDL synthesizable design; and further comprising the step of: configuring in the HDL synthesizable design an interface for the gate-level hardware representation.
 14. The method of claim 13 , further comprising the steps of: determining the presence of any C-type pointers in the C-type program; and compiling any C-type pointers and pointer indirection into an HDL state-machine-based memory access protocol.
 15. The method of claim 13 , further comprising the steps of: determining the presence of any non-addressable variables in the C-type program; and mapping any non-addressable variables onto hardware registers formed in HDL.
 16. The method of claim 13 , further comprising the steps of: determining the presence of any addressable variables in the C-type program; and mapping any addressable variables onto at least one of addressable hardware memory and an addressable array of hardware registers formed in HDL.
 17. The method of claim 13 , fuirther comprising the steps of determining the presence of any complicated C-type mathematical operations in the C-type program; and compiling multiple occurrences of any complicated C-type mathematical operation into a given HDL functional block that implements such an operation invoked on each occurrence by different states driven by the state machine.
 18. The method of claim 13 wherein a plurality of selected C-type functions that can execute simultaneously are compiled into a plurality of HDL state machines that operate in parallel.
 19. The method of claim 13 wherein a plurality of interdependent C-type functions are compiled into a plurality of executable HDL program language expressions that operate one of simultaneously and sequentially in a data processing pipeline.
 20. The method of claim 13 wherein a callable C-type function is compiled into at least one executable HDL state machine which is executed one of synchronously and asynchronously on the occurrence of an external event.
 21. The method of claim 15 wherein the C-type programming language variables include at least one of integer, floating point, pointer, enum, struct, and union variables.
 22. The method of claim 16 wherein the C-type programming language variables include at least one of integer, floating point, pointer, enum, struct, and union variables.
 23. The method of claim 13 , further comprising the step of compiling C-type progranmming language structure assignment, structure function parameters, and structure function return values into HDL synthesizable expressions.
 24. The method of claim 13 , further comprising the step of determining the presence of any recursion in the C-type program, and wherein at least one of an identifiable direct and indirect recursive function call is compiled into an HDL state machine which has an interface to a stack implemented utilizing one of external and internal memory and an array of hardware registers, wherein the state machine has a stack pointer implemented utilizing a hardware register employed to store and restore local variables of the recursive function and other recursive function information in the stack.
 25. A method for converting a high-level language program to a hardware design, comprising the steps of: creating an algorithmic representation in a given high-level programming language corresponding to a preliminary hardware design; translating the high-level programming language preliminary hardware design into a C-type programming language preliminary hardware design; and compiling the C-type programming language preliminary hardware design into a hardware description language (HDL) synthesizable design.
 26. The method of claim 25 , further comprising the step of synthesizing the HDL design into a gate-level hardware representation using a synthesis program to interpret the HDL design.
 27. The method of claim 26 , further comprising the step of using physical design tools to implement the gate-level hardware representation as an actual hardware implementation.
 28. The method of claim 25 wherein the high-level programming language is selected from among the group of C-type programming languages consisting of APL, Ada, Algol, B, Basic, Kernighan & Ritchie C, C++, CLOS, COBOL, Clu, Common Lisp, Coral, Dylan, Eiffel, Emacs Lisp, Forth, Fortran, IDL, Icon, Java, Jovial, Lisp, LOGO, ML, Modula, Oberon, Objective C, PL/I, PL/M, Pascal, Postscript, Prolog, Python, RTL, Rexx, SETL, Simula, Sather, Scheme, Smalltalk, Standard ML, TCL, and TRAC.
 29. The method of claim 25 wherein the hardware description language is selected from among the group of hardware description languages consisting of Verilog, VHDL, ABBL, CUPL, AHDL, MACHX, and PALASM.
 30. The method of claim 25 , further comprising the step of simulating the HDL synthesizable design.
 31. The method of claim 25 wherein the step of compiling comprises the steps of: mapping predetermined C-type programming language expressions to functionally equivalent HDL program language expressions; and assigning input/output as defined in the C-type program to specific wires in the HDL synthesizable design; and further comprising the step of: configuring in the HDL synthesizable design an interface for the gate-level hardware representation.
 32. The method of claim 31 wherein a plurality of selected C-type functions that can execute simultaneously are compiled into a plurality of executable HDL program language expressions that operate in parallel.
 33. The method of claim 31 wherein a plurality of interdependent C-type functions are compiled into a plurality of executable HDL program language expressions that operate one of simultaneously and sequentially in a data processing pipeline.
 34. The method of claim 31 wherein a callable C-type function is compiled into an executable HDL program language expression that is executed one of synchronously and asynchronously on the occurrence of an external event.
 35. The method of claim 31 wherein the C-type programm-ing language expressions include at least one of integer, floating point, pointer, enum, struct, and union variables.
 36. The method of claim 31 , further comprising the step of compiling C-type programming language structure assignment, structure function parameters, and structure function return values into HDL synthesizable expressions.
 37. The method of claim 25 wherein the step of compiling comprises the steps of: compiling a C-type program control flow into an HDL state machine; and assigning input/output as defined in the C-type program to specific wires in the HDL synthesizable design; and further comprising the step of: configuring in the HDL synthesizable design an interface for the gate-level hardware representation.
 38. The method of claim 37 , further comprising the steps of: determining the presence of any C-type pointers in the C-type program; and compiling any C-type pointers and pointer indirection into an HDL state-machine-based memory access protocol.
 39. The method of claim 37 , further comprising the steps of: determining the presence of any non-addressable variables in the C-type program; and mapping any non-addressable variables ont o h ardware registers formed in HDL.
 40. The method of claim 37 , further comprising the steps of: determining the presence of any addressable variables in the C-type program; and mapping any addressable variables onto at least one of addressable hardware memory and an addressable array of hardware registers formed in HDIL.
 41. The method of claim 37 , further comprising the steps of: determining the presence of any complicated C-type mathematical operations in the C-type program; and compiling multiple occurrences of any complicated C-type mathematical operation into a given HDL fulnctional block that implements such an operation invoked on each occurrence by different states driven by the state machine.
 42. The method of claim 37 wherein a plurality of selected C-type functions that can execute simultaneously are compiled into a plurality of HDL state machines that operate in parallel.
 43. The method of claim 37 wherein a plurality of interdependent C-type functions are compiled into a plurality of executable HDL program language expressions that operate one of simultaneously and sequentially in a data processing pipeline.
 44. The method of claim 37 wherein a callable C-type function is compiled into at least one executable HDL state machine which is executed one of synchronously and asynchronously on the occurrence of an external event.
 45. The method of claim 39 wherein the C-type programming language variables include at least one of integer, floating point, pointer, enum, struct, and union variables.
 46. The method of claim 40 wherein the C-type programming language variables include at least one of integer, floating point, pointer, enum, struct, and union variables.
 47. The method of claim 37 , further comprising the step of compiling C-type programming language structure assignment, structure function parameters, and structure function return values into HDL synthesizable expressions.
 48. The method of claim 37 , further comprising the step of determining the presence of any recursion in the C-type program, and wherein at least one of an identifiable direct and indirect recursive function call is compiled into an HDL state machine which has an interface to a stack implemented utilizing one of external and internal memory and an array of hardware registers, wherein the state machine has a stack pointer implemented utilizing a hardware register employed to store and restore local variables of the recursive function and other recursive function information in the stack.
 49. A method for converting a high-level algorithmic programming language program to a hardware design description, comprising the steps of: selecting a given high-level algorithmic programming language having at least one of pointers and structures; creating an algorithmic representation in the given high-level algorithmic programming language corresponding to a preliminary hardware design; and compiling the high-level programming language preliminary hardware design into hardware-specific descriptions for a hardware implementation.
 50. The method of claim 49 wherein the step of compiling comprises the step of compiling the high-level algorithmic programming language preliminary hardware design into a hardware design language (HDL) synthesizable design.
 51. The method of claim 50 , further comprising the step of synthesizing the HDL design into a gate-level hardware representation using a synthesis program to interpret the HDL design.
 52. The method of claim 51 , further comprising the step of using physical design tools to implement the gate-level representation as an actual hardware implementation.
 53. The method of claim 49 wherein the high-level algorithmic programming language is selected from among the group of C-type programming languages consisting of APL, Ada, Algol, ANSI C, B, Basic, Kernighan & Ritchie C, C++, CLOS, COBOL, Clu, Common Lisp, Coral, Dylan, Eiffel, Emacs Lisp, Forth, Fortran, IDL, Icon, Java, Jovial, Lisp, LOGO, ML, Modula, Oberon, Objective C, PL/I, PL/M, Pascal, Postscript, Prolog, Python, RTL, Rexx, SETL, Simula, Sather, Scheme, Smalltalk, Standard ML, TCL, and TRAC.
 54. The method of claim 50 wherein the hardware design language is selected from among the group of hardware design languages consisting of Verilog, VHDL, ABEL, CUPL, AHDL, MACHX, and PALASM.
 55. The method of claim 50 , further comprising the step of simulating the HDL synthesizable design. 